Design and implementation of the FPGA-based chaotic van der pol oscillator

Year 2018, Volume: 2 Issue: 3, 309 - 314, 15.12.2018

Mustafa Dursun Elif Kaşifoğlu

Abstract

In this study, the chaotic
Van der Pol system was implemented for real-time chaos applications on FPGA
chip. The chaotic Van der Pol system was also modelled numerically by using the
Euler algorithm ODE (Ordinary Differential Equation) solver on Matlab.
Numerical structure of the chaotic Van der Pol oscillator designed on Matlab was
taken as reference for the design of FPGA-based chaotic Van der Pol oscillator
unit. The chaotic Van der Pol system was coded in Very High-Speed Integrated
Circuits Hardware Description Language (VHDL) with 32-bit IEEE-754-1985
floating point number standard. The designed chaotic Van der Pol system was
synthesized in the Xilinx ISE Project Navigator program and was implemented on
the Xilinx VIRTEX-6 chip family, XC6VLX75T device, FF784 package. The maximum
operating frequency of the FPGA-based chaotic Van der Pol oscillator unit
obtained from Place and Route processes was 498.728 MHz. Additionally, chip
statistics of the FPGA-based Van der Pol oscillator were presented.

Keywords

FPGA Chips, Van Der Pol Oscillator, VHDL, Euler Algorith, Chaotic Systems

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